1. Field of the Invention
The invention relates to a method of correcting layout pattern, and more particularly, to a method of correcting layout pattern with no blind spot.
2. Description of the Prior Art
Critical technologies such as the photolithography and etching technologies are frequently used in semiconductor manufacturing processes. The photolithography technology usually involves transferring a complicated integrated circuit pattern to a semiconductor wafer surface for steps such as etching and implantation. These patterns must be extremely accurate for forming delicate integrated circuits so as to align with the patterns of the previous and following steps.
In the photolithographic step, deviations often occur and jeopardize the performance of the semiconductor device when the patterns on the masks are transferred onto the wafer surface. Such deviations are usually related with the characters of the patterns to be transferred, the topology of the wafer, the source of the light and various process parameters.
There are many known verification methods, correction methods and compensation methods for the deviations caused by the optical proximity effect, process rules (PRC) and lithography rules (LRC) to improve the image quality after transfer. Some of the known methods are called optical proximity correction (OPC), process rule check (PRC) and lithography rule check (LRC). The commercially available OPC software may test problems such as pitch, bridge, and critical dimension uniformity in the layout patterns. Such software may correct the standard layout patterns on the masks using the theoretical image, so as to obtain correctly exposed image patterns on the wafers. Such methods not only test problems in the layout patterns but also correct the layout patterns on the masks using the theoretical image. If the corrected image patterns are useable, they are output for the fabrication of masks to obtain the correct image patterns on the wafer.
Generally speaking, there are well-established stand operational procedures available for the reference of the above-mentioned verification, correction and compensation methods. For example, the conventional procedure using optical proximity correction to verify the layout patterns on a mask may be first inputting a layout pattern. Then the Boolean pre-treatment of OPC is performed on the layout pattern to obtain a preliminary layout pattern. An OPC is conducted thereafter by using a variety of commercial optical proximity correction software, which can correct the mask pattern theoretically to acquire more correct pattern on a wafer.
A mask pattern corrected by the optical proximity correction must be inspected by a process rule check (PRC) to confirm the correctness of the mask pattern. If the corrected mask pattern completely obeys the rules of the process rule check, the mask pattern is then output and provided to a mask for lithography process. Conversely, if a portion or all portions of the mask pattern violates the rules of process rule check, the mask pattern needs to be re-modified and verified. The process rule check (PRC) inspects line ends and corners of each segment of a mask pattern to verify that if those geometrical patterns obey the limitation of the critical width and the critical space of the designed integrated circuit layout.
However, the aforementioned inspection typically inspects a target pattern from a 45 degree approach, such as from 0-45 degree, 45-90 degree, 90-135 degree, or 135-180 degree. The 45 degree based inspection often creates a blind spot between every 45 degree angle and limits the correction process from outputting a precise layout pattern.